Self-testing checker design for arbitrary number of code words of (m,n) code

Yu B. Burkatovskaya, N. B. Butorina, A. Yu Matrosova

Результат исследований: Материалы для книги/типы отчетовМатериалы для конференции

3 Цитирования (Scopus)

Аннотация

FPGA technology is used to provide self-testing checker (STC) design based on ability of each LUT to implement any Boolean function of the fixed number of variables and applying two outputs CLBs consisting of two LUTs. A universal decomposition synthesis method of STC for subset of all code words (arbitrary number L of code words) of (m, n) code is suggested. It is based on separating the proper essential subtrees from the tree representing all code words of (m,n) code. Self-testing property is proved for a set V of faults including multiple stuck-at faults at each CLB input and output poles. As a rule complexity of a self-testing checker for an arbitrary number of code words of (m, n) code is less than complexity of a self-testing checker for all code words of the same (m, n) code.

Язык оригиналаАнглийский
Название основной публикацииBEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference
Страницы183-186
Число страниц4
DOI
СостояниеОпубликовано - 2006
СобытиеBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference - Tallinn, Эстония
Продолжительность: 2 окт 20064 окт 2006

Другое

ДругоеBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference
СтранаЭстония
ГородTallinn
Период2.10.064.10.06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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