Self-testing checker design for arbitrary number of code words of (m,n) code

Yu B. Burkatovskaya, N. B. Butorina, A. Yu Matrosova

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

FPGA technology is used to provide self-testing checker (STC) design based on ability of each LUT to implement any Boolean function of the fixed number of variables and applying two outputs CLBs consisting of two LUTs. A universal decomposition synthesis method of STC for subset of all code words (arbitrary number L of code words) of (m, n) code is suggested. It is based on separating the proper essential subtrees from the tree representing all code words of (m,n) code. Self-testing property is proved for a set V of faults including multiple stuck-at faults at each CLB input and output poles. As a rule complexity of a self-testing checker for an arbitrary number of code words of (m, n) code is less than complexity of a self-testing checker for all code words of the same (m, n) code.

Original languageEnglish
Title of host publicationBEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference
Pages183-186
Number of pages4
DOIs
Publication statusPublished - 2006
EventBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference - Tallinn, Estonia
Duration: 2 Oct 20064 Oct 2006

Other

OtherBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference
CountryEstonia
CityTallinn
Period2.10.064.10.06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Burkatovskaya, Y. B., Butorina, N. B., & Matrosova, A. Y. (2006). Self-testing checker design for arbitrary number of code words of (m,n) code. In BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference (pp. 183-186). [4100314] https://doi.org/10.1109/BEC.2006.311093