Abstract
This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.
Original language | English |
---|---|
Article number | 6314491 |
Pages (from-to) | 621-624 |
Number of pages | 4 |
Journal | IEEE Transactions on Power Electronics |
Volume | 28 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1 Jan 2013 |
Externally published | Yes |
Keywords
- Ageing
- current limiter
- junction gate field-effect transistors (JFETs)
- short circuit
- silicon carbide
ASJC Scopus subject areas
- Electrical and Electronic Engineering