Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors

M. Berkani, S. Lefebvre, Z. Khatir

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.

Original languageEnglish
Article number6314491
Pages (from-to)621-624
Number of pages4
JournalIEEE Transactions on Power Electronics
Volume28
Issue number2
DOIs
Publication statusPublished - 1 Jan 2013
Externally publishedYes

Fingerprint

Junction gate field effect transistors
Short circuit currents
Transistors
Aging of materials
Metals
Degradation
Electric potential

Keywords

  • Ageing
  • current limiter
  • junction gate field-effect transistors (JFETs)
  • short circuit
  • silicon carbide

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors. / Berkani, M.; Lefebvre, S.; Khatir, Z.

In: IEEE Transactions on Power Electronics, Vol. 28, No. 2, 6314491, 01.01.2013, p. 621-624.

Research output: Contribution to journalArticle

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