Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors

Abstract

This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.

Original language	English
Article number	6314491
Pages (from-to)	621-624
Number of pages	4
Journal	IEEE Transactions on Power Electronics
Volume	28
Issue number	2
DOIs	https://doi.org/10.1109/TPEL.2012.2215629
Publication status	Published - 1 Jan 2013
Externally published	Yes

Keywords

Ageing
current limiter
junction gate field-effect transistors (JFETs)
short circuit
silicon carbide

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TPEL.2012.2215629

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Berkani, M., Lefebvre, S., & Khatir, Z. (2013). Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors. IEEE Transactions on Power Electronics, 28(2), 621-624. [6314491]. https://doi.org/10.1109/TPEL.2012.2215629

@article{1a14be43c5a94780a618847d2319296f,

title = "Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors",

abstract = "This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.",

keywords = "Ageing, current limiter, junction gate field-effect transistors (JFETs), short circuit, silicon carbide",

author = "M. Berkani and S. Lefebvre and Z. Khatir",

year = "2013",

month = jan,

day = "1",

doi = "10.1109/TPEL.2012.2215629",

language = "English",

volume = "28",

pages = "621--624",

journal = "IEEE Transactions on Power Electronics",

issn = "0885-8993",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Saturation current and on-resistance correlation during during repetitive short-circuit conditions on SiC JFET transistors

AU - Berkani, M.

AU - Lefebvre, S.

AU - Khatir, Z.

PY - 2013/1/1

Y1 - 2013/1/1

N2 - This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.

AB - This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.

KW - Ageing

KW - current limiter

KW - junction gate field-effect transistors (JFETs)

KW - short circuit

KW - silicon carbide

UR - http://www.scopus.com/inward/record.url?scp=84867181904&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84867181904&partnerID=8YFLogxK

U2 - 10.1109/TPEL.2012.2215629

DO - 10.1109/TPEL.2012.2215629

M3 - Article

AN - SCOPUS:84867181904

VL - 28

SP - 621

EP - 624

JO - IEEE Transactions on Power Electronics

JF - IEEE Transactions on Power Electronics

SN - 0885-8993

IS - 2

M1 - 6314491

ER -