TY - JOUR
T1 - On the self-testing (m,n)-code checker design
AU - Butorina, N.
AU - Burkatovskaya, Yu
AU - Pakhomova, E.
N1 - Publisher Copyright:
© 2021 Institute of Physics Publishing. All rights reserved.
Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2021/1/20
Y1 - 2021/1/20
N2 - We propose an approach to a self-testing (m, n)-code checker design, based on subdividing the set of all code words into special subsets called segments. The checker circuit is constructed by using one- and two-output configurable logic blocks (CLB). Previously, in each output of a CLB, a function representing exactly one segment was implemented. In the proposed approach, at each CLBs output, it is possible to implement functions that represent several segments and to provide the self-testing property. It allows reducing the number of CLBs and simplifying the circuit of the checker.
AB - We propose an approach to a self-testing (m, n)-code checker design, based on subdividing the set of all code words into special subsets called segments. The checker circuit is constructed by using one- and two-output configurable logic blocks (CLB). Previously, in each output of a CLB, a function representing exactly one segment was implemented. In the proposed approach, at each CLBs output, it is possible to implement functions that represent several segments and to provide the self-testing property. It allows reducing the number of CLBs and simplifying the circuit of the checker.
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U2 - 10.1088/1757-899X/1019/1/012098
DO - 10.1088/1757-899X/1019/1/012098
M3 - Conference article
AN - SCOPUS:85100343387
VL - 1019
JO - IOP Conference Series: Materials Science and Engineering
JF - IOP Conference Series: Materials Science and Engineering
SN - 1757-8981
IS - 1
M1 - 012098
T2 - 14th International Forum on Strategic Technology, IFOST 2019
Y2 - 14 October 2019 through 17 October 2019
ER -