Influence of gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode

Stephane Lefebvre, Francois Costa, Francis Miserey

Research output: Contribution to journalArticle

Abstract

In order to use a power MOS transistor in the ZVS mode at high switching frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics available in the datasheets have to be completed if necessary to choose the ideal transistor for application with minimal losses, and additional characterizations have to be realized in order to specify or complete the datasheets. In particular, it is necessary to be sure that all the cells of the MOS transistor can be opened in a short time before the voltage rise time at turn-off, in order to reduce as low as possible turn-off losses. The paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and is useful to choose a MOS transistor having minimal losses in very high switching frequency ZVS applications.

Original languageEnglish
Pages (from-to)1606-1611
Number of pages6
JournalPESC Record - IEEE Annual Power Electronics Specialists Conference
Volume3
DOIs
Publication statusPublished - 1 Jan 2000
Externally publishedYes

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ASJC Scopus subject areas

  • Modelling and Simulation
  • Condensed Matter Physics
  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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