Abstract
In order to use a power MOS transistor in the ZVS mode at high switching frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics available in the datasheets have to be completed if necessary to choose the ideal transistor for application with minimal losses, and additional characterizations have to be realized in order to specify or complete the datasheets. In particular, it is necessary to be sure that all the cells of the MOS transistor can be opened in a short time before the voltage rise time at turn-off, in order to reduce as low as possible turn-off losses. The paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and is useful to choose a MOS transistor having minimal losses in very high switching frequency ZVS applications.
| Original language | English |
|---|---|
| Pages (from-to) | 1606-1611 |
| Number of pages | 6 |
| Journal | PESC Record - IEEE Annual Power Electronics Specialists Conference |
| Volume | 3 |
| DOIs | |
| Publication status | Published - 1 Jan 2000 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Modelling and Simulation
- Condensed Matter Physics
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
Cite this
Influence of gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode. / Lefebvre, Stephane; Costa, Francois; Miserey, Francis.
In: PESC Record - IEEE Annual Power Electronics Specialists Conference, Vol. 3, 01.01.2000, p. 1606-1611.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Influence of gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode
AU - Lefebvre, Stephane
AU - Costa, Francois
AU - Miserey, Francis
PY - 2000/1/1
Y1 - 2000/1/1
N2 - In order to use a power MOS transistor in the ZVS mode at high switching frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics available in the datasheets have to be completed if necessary to choose the ideal transistor for application with minimal losses, and additional characterizations have to be realized in order to specify or complete the datasheets. In particular, it is necessary to be sure that all the cells of the MOS transistor can be opened in a short time before the voltage rise time at turn-off, in order to reduce as low as possible turn-off losses. The paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and is useful to choose a MOS transistor having minimal losses in very high switching frequency ZVS applications.
AB - In order to use a power MOS transistor in the ZVS mode at high switching frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics available in the datasheets have to be completed if necessary to choose the ideal transistor for application with minimal losses, and additional characterizations have to be realized in order to specify or complete the datasheets. In particular, it is necessary to be sure that all the cells of the MOS transistor can be opened in a short time before the voltage rise time at turn-off, in order to reduce as low as possible turn-off losses. The paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and is useful to choose a MOS transistor having minimal losses in very high switching frequency ZVS applications.
UR - http://www.scopus.com/inward/record.url?scp=0034474008&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0034474008&partnerID=8YFLogxK
U2 - 10.1109/PESC.2000.880545
DO - 10.1109/PESC.2000.880545
M3 - Article
AN - SCOPUS:0034474008
VL - 3
SP - 1606
EP - 1611
JO - PESC Record - IEEE Annual Power Electronics Specialists Conference
JF - PESC Record - IEEE Annual Power Electronics Specialists Conference
SN - 0275-9306
ER -