The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check-pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.
|Journal||Journal of Physics: Conference Series|
|Publication status||Published - 2017|
|Event||International Conference on Information Technologies in Business and Industry 2016 - Tomsk, Russian Federation|
Duration: 21 Sep 2016 → 23 Sep 2016
ASJC Scopus subject areas
- Physics and Astronomy(all)