FPGA design of the fast decoder for burst errors correction

E. A. Mytsko, A. N. Malchukov, I. V. Zoev, S. E. Ryzhova, V. L. Kim

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)


The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check-pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.

Original languageEnglish
Article number012105
JournalJournal of Physics: Conference Series
Issue number1
Publication statusPublished - 2017
EventInternational Conference on Information Technologies in Business and Industry 2016 - Tomsk, Russian Federation
Duration: 21 Sep 201623 Sep 2016

ASJC Scopus subject areas

  • Physics and Astronomy(all)

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