Finding False Paths in Sequential Circuits

Y. Маtrosova, V. V. Аndreeva, S. V. Chernyshov, S. V. Rozhkova, D. V. Kudin

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.

Original languageEnglish
Pages (from-to)1-8
Number of pages8
JournalRussian Physics Journal
DOIs
Publication statusAccepted/In press - 8 Feb 2018

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logic circuits
equivalent circuits
diagrams

Keywords

  • equivalent normal form
  • false path
  • path delay fault
  • reduced ordered binary decision diagram (ROBDD)
  • sequential circuit

ASJC Scopus subject areas

  • Physics and Astronomy(all)

Cite this

Маtrosova, Y., Аndreeva, V. V., Chernyshov, S. V., Rozhkova, S. V., & Kudin, D. V. (Accepted/In press). Finding False Paths in Sequential Circuits. Russian Physics Journal, 1-8. https://doi.org/10.1007/s11182-018-1290-0

Finding False Paths in Sequential Circuits. / Маtrosova, Y.; Аndreeva, V. V.; Chernyshov, S. V.; Rozhkova, S. V.; Kudin, D. V.

In: Russian Physics Journal, 08.02.2018, p. 1-8.

Research output: Contribution to journalArticle

Маtrosova, Y. ; Аndreeva, V. V. ; Chernyshov, S. V. ; Rozhkova, S. V. ; Kudin, D. V. / Finding False Paths in Sequential Circuits. In: Russian Physics Journal. 2018 ; pp. 1-8.
@article{4483f83cc08640578c80c592892918d8,
title = "Finding False Paths in Sequential Circuits",
abstract = "Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.",
keywords = "equivalent normal form, false path, path delay fault, reduced ordered binary decision diagram (ROBDD), sequential circuit",
author = "Y. Маtrosova and Аndreeva, {V. V.} and Chernyshov, {S. V.} and Rozhkova, {S. V.} and Kudin, {D. V.}",
year = "2018",
month = "2",
day = "8",
doi = "10.1007/s11182-018-1290-0",
language = "English",
pages = "1--8",
journal = "Russian Physics Journal",
issn = "1064-8887",
publisher = "Consultants Bureau",

}

TY - JOUR

T1 - Finding False Paths in Sequential Circuits

AU - Маtrosova, Y.

AU - Аndreeva, V. V.

AU - Chernyshov, S. V.

AU - Rozhkova, S. V.

AU - Kudin, D. V.

PY - 2018/2/8

Y1 - 2018/2/8

N2 - Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.

AB - Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.

KW - equivalent normal form

KW - false path

KW - path delay fault

KW - reduced ordered binary decision diagram (ROBDD)

KW - sequential circuit

UR - http://www.scopus.com/inward/record.url?scp=85041525636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85041525636&partnerID=8YFLogxK

U2 - 10.1007/s11182-018-1290-0

DO - 10.1007/s11182-018-1290-0

M3 - Article

SP - 1

EP - 8

JO - Russian Physics Journal

JF - Russian Physics Journal

SN - 1064-8887

ER -