Failure modes and robustness of SiC JFET transistors under current limiting operations

Mounira Bouarroudj-Berkani, Stéphane Lefebvre, Dhouha Othman, Sabrine Moumen Sabrine, Zoubir Khatir, Tarek Ben Salah

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators.

Original languageEnglish
Title of host publicationProceedings of the 2011 14th European Conference on Power Electronics and Applications, EPE 2011
Publication statusPublished - 11 Oct 2011
Externally publishedYes
Event2011 14th European Conference on Power Electronics and Applications, EPE 2011 - Birmingham, United Kingdom
Duration: 30 Aug 20111 Sep 2011

Publication series

NameProceedings of the 2011 14th European Conference on Power Electronics and Applications, EPE 2011

Conference

Conference2011 14th European Conference on Power Electronics and Applications, EPE 2011
CountryUnited Kingdom
CityBirmingham
Period30.8.111.9.11

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Keywords

  • Current limiter
  • JFET
  • Power semiconductor
  • Robustness
  • Short circuit
  • Silicon Carbide

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Bouarroudj-Berkani, M., Lefebvre, S., Othman, D., Sabrine, S. M., Khatir, Z., & Salah, T. B. (2011). Failure modes and robustness of SiC JFET transistors under current limiting operations. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications, EPE 2011 [6020356] (Proceedings of the 2011 14th European Conference on Power Electronics and Applications, EPE 2011).