Abstract
The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2 kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density dissipated by the chip and the simulated 1D-thermal junction. Finally, the chips of the devices which failed in a “fail-to-open” mode have been studied in order to find the physical reasons of this original and unusual fail-safe mode.
| Original language | English |
|---|---|
| Pages (from-to) | 598-603 |
| Number of pages | 6 |
| Journal | Microelectronics Reliability |
| Volume | 88-90 |
| DOIs | |
| Publication status | Published - 1 Sep 2018 |
| Externally published | Yes |
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Keywords
- Failure analysis
- Failure mode
- Power MOSFET
- Reliability
- Short-circuit
- Silicon Carbide (SiC)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Safety, Risk, Reliability and Quality
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering
Cite this
Ensure an original and safe “fail-to-open” mode in planar and trench power SiC MOSFET devices in extreme short-circuit operation. / Boige, F.; Richardeau, F.; Lefebvre, S.; Blaquière, J. M.; Guibaud, G.; Bourennane, A.
In: Microelectronics Reliability, Vol. 88-90, 01.09.2018, p. 598-603.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Ensure an original and safe “fail-to-open” mode in planar and trench power SiC MOSFET devices in extreme short-circuit operation
AU - Boige, F.
AU - Richardeau, F.
AU - Lefebvre, S.
AU - Blaquière, J. M.
AU - Guibaud, G.
AU - Bourennane, A.
PY - 2018/9/1
Y1 - 2018/9/1
N2 - The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2 kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density dissipated by the chip and the simulated 1D-thermal junction. Finally, the chips of the devices which failed in a “fail-to-open” mode have been studied in order to find the physical reasons of this original and unusual fail-safe mode.
AB - The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2 kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density dissipated by the chip and the simulated 1D-thermal junction. Finally, the chips of the devices which failed in a “fail-to-open” mode have been studied in order to find the physical reasons of this original and unusual fail-safe mode.
KW - Failure analysis
KW - Failure mode
KW - Power MOSFET
KW - Reliability
KW - Short-circuit
KW - Silicon Carbide (SiC)
UR - http://www.scopus.com/inward/record.url?scp=85054824798&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85054824798&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2018.07.026
DO - 10.1016/j.microrel.2018.07.026
M3 - Article
VL - 88-90
SP - 598
EP - 603
JO - Microelectronics Reliability
JF - Microelectronics Reliability
SN - 0026-2714
ER -