Ageing of SiC JFET transistors under repetitive current limitation conditions

M. Bouarroudj-Berkani, D. Othman, S. Lefebvre, S. Moumen, Z. Khatir, T. Ben Sallah

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

In power applications using normally on transistors, short circuit or current limitation modes can be recurrent during operation, especially when powering converters. So, studying the robustness of these devices under such severe condition is an important issue. The paper presents ageing tests of normally on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit operations. Experimental tests are detailed and the evolution of electrical parameters during ageing is presented. Especially, the evolution during tests of ageing indicators like on-state resistance and saturation current is presented. Numerical investigations have been performed in order to estimate temperature during short circuit operation and to quantify the effect of the maximum temperature on the ageing process.

Original languageEnglish
Pages (from-to)1532-1537
Number of pages6
JournalMicroelectronics Reliability
Volume50
Issue number9-11
DOIs
Publication statusPublished - 1 Sep 2010
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Ageing of SiC JFET transistors under repetitive current limitation conditions'. Together they form a unique fingerprint.

  • Cite this

    Bouarroudj-Berkani, M., Othman, D., Lefebvre, S., Moumen, S., Khatir, Z., & Ben Sallah, T. (2010). Ageing of SiC JFET transistors under repetitive current limitation conditions. Microelectronics Reliability, 50(9-11), 1532-1537. https://doi.org/10.1016/j.microrel.2010.07.035